The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Electronic devices use integrated circuits including memory to store data. One type of memory that is commonly used in electronic devices is dynamic random-access memory (DRAM). DRAM stores each bit of data in a separate capacitor within the integrated circuit. The capacitor can be either charged or discharged, which represents the two values of a bit. Since non-conducting transistors leak, the capacitors will slowly discharge, and the information eventually fades unless the capacitor charge is refreshed periodically.
Each DRAM cell includes a transistor and a capacitor as compared to four or six transistors in static RAM (SRAM). This allows DRAM to reach very high storage densities. Unlike flash memory, DRAM is volatile memory (vs. non-volatile memory), since data is lost when power is removed.
Several emerging memory devices are potential replacements for DRAM. For example, DRAM replacements include non-volatile RAM (NVRAM) devices such as resistive RAM (RRAM or ReRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FRAM or FeRAM), spin-transfer torque RAM (STT-RAM), and phase-change RAM (PC-RAM). While the following description refers to STT-RAM, the description applies to other types of NVRAM devices.
Substrate processing systems are used to deposit and etch layers of film on substrates such as a semiconductor wafer. Photoresist and/or hard mask layers may be used during processing to protect underlying layers of the semiconductor wafer during etching. After metal etching is complete, the photoresist and/or hard mask layers are removed. In some situations, the photoresist or hard mask layers may not fully protect underlying layers during metal etching and/or cleaning and portions of one or more of the underlying layers may be damaged, which may cause defects in the layer materials or may cause deficiencies in the memory device.
Referring now to FIGS. 1A to 1C, an example of an MRAM etch sequence is shown. In FIG. 1A, an MRAM stack 10 includes a substrate 14, an oxide layer 18, a bottom electrode 22, a fixed magnetic layer 26, a magnetic tunnel junction (MTJ) layer 30, a free magnetic layer 32, a top electrode 34, and a photoresist mask 38. In FIG. 1B, the MRAM stack 10 is shown after etching of the top electrode 34 and the free magnetic layer 32. In FIG. 1C, a hard mask 42 is deposited over the free magnetic layer 32, the top electrode 34 and the photoresist mask 38. In subsequent steps, the hard mask 42 is used to etch the remaining layers including the oxide layer 18, the bottom electrode 22, the fixed magnetic layer 26 and the MTJ 30.
Referring now to FIG. 2, an example of an SST-RAM stack 50 is shown. The STT-RAM stack 50 may include non-volatile metals that are difficult to etch. The STT-RAM stack 50 includes a bottom electrode 52 including combinations of tantalum (Ta) and/or tantalum nitride (TaN). The STT-RAM stack 50 further includes a fixed or pinned magnetic multi-layer 54 including combinations of platinum (Pt), manganese (Mn), cobalt (Co), iron (Fe), and ruthenium (Ru). The STT-RAM stack 50 further includes a free magnetic multi-layer 60 that includes combinations of nickel (Ni), Fe, Co, palladium (Pd), boron (B) and Ru. The STT-RAM stack 50 further includes a top electrode 62 including Ta and/or TaN. The multi-layers are deposited as thin films and etched to form a vertical pillar. This is just one example and other material combinations are possible for SU-RAM stacks.
The two magnetic multi-layers are separated from each other by a MTJ layer 66 that is typically made of a dielectric material such as magnesium oxide (MgO) or aluminum oxide (Al2O3). The dielectric material used for the MTJ layer 66 may be a very high-quality and crystalline dielectric material through which the spin-polarized current travels to switch magnetization of the free magnetic multilayer 60. The dielectric material used for the MTJ layer 66 can be etched or otherwise damaged by exposure to plasma etch species such as halides, oxygen, hydrogen or other etchants. Also, the materials in the STT-RAM stack 50 can be degraded when exposed to moisture and aqueous processes. For example, Fe-containing layers (or other easily oxidized metals) may be degraded when exposed to oxygen, moisture or other aqueous processes. The dielectric material used for the MTJ layer 66 is also sensitive to any sidewall deposition during etching because metallic deposits can lead to short circuits.
Because the metal-containing layers in STT-RAM stack 50 and the MTJ layer 66 are sensitive to damage, a limited number of processes and chemicals can be used during the metal etching and/or cleaning steps required to create the vertical pillar. Typical chemical limitations include no halides, hydrogen, oxygen, or aqueous solutions. The chemical limitations eliminate many of the common chemicals used for metal etch or dielectric deposition processes. Furthermore, it is often desirable to have an integrated deposition and etch system so that the stack can be encapsulated before exposure to air.